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EE2169 Laboratory for Digital Systems Design I

These WIKI pages provide general, assignment, and supplemental information for the laboratory sections of EE2369, Digital Systems Design I.

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ANNOUNCEMENT WEEKS of 3/28/2016 to 4/8/2016:

TO COMPLETE LAB 6 PLEASE USE THE HEADER FILE AND CONSTRAINTS FILE UNDER THE LAB 6 HANDOUT SECTION.

YOU WILL BE COMPLETING LAB 6 BY NEXT WEEK AND START WORKING ON LAB 7 NEXT WEEK TOO. 

MORE INFORMATION ON LAB 7 WILL BE AVAILABLE BY THE END OF THIS WEEK.

 

ANNOUNCEMENT WEEK of 2/15/2016 to 2/19/2016:

 

THIS WEEK THERE WON’T BE LAB SESSIONS ON WEDNESDAY. HOWEVER, YOU CAN SHOW UP TO ANY REMINDER SESSIONS TO CATCHUP WITH LABS 1, 2 AND 3.

 

TUESDAY (2/16/2016)          10:30 am – 1:20 pm AND 1:30 pm – 4:20 pm

 

FRIDAY (2/19/2016)             10:30 am – 1:20 pm

WE WILL BE ACCEPTING DEMONSTRATIONS FOR LAB 2 (SWITCHES) AND 3 (LABVIEW) AND GRADE THE NOTEBOOK UP TO LAB 2. YOU CAN SHOW YOUR NOTEBOOK WORK ON LAB 3 IF YOU FINISH IT BUT IS NOT MANDATORY. BY NEXT WEEK WE WILL JUST GRADE LAB 3 AND YOU WILL START WORKING AND DEMONSTRATING LAB 3B (XILINX SCHEMATIC).


NOTE FOR LAB 3 (WEEK 2/8/2016-2/12/2016):  STUDENTS YOU NEED TO WORK ON THE PRELAB 3 BUT IS NOT MANDATORY TO SUBMIT IT. WE WILL GIVE FURTHER DETAILS DURING THE LAB SESSION.

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ANNOUNCEMENT (1/25/2016) - Welcome to the Digital Systems Design I laboratory for Spring 2016

 

Laboratory Information

Syllabus Spring2016

Laboratory Assignments

Lab 1

Lab 2

Lab 3

Lab 3B

Lab 4 - Numeric Braille Printer

Lab 5 - Numeric Braille Printer Verilog & VHDL

Lab5 Verilog Header (.v file)

Lab5 VHDL Header (.vhd file)

Lab 6 - Decoder/Adder

LAB6 Verilog Header (.v file)

Lab6 Constraints (.ucf file)

Lab7 – Add-Sub and Transmitter

Lab7 Part B Constraints (.ucf)

Lab 8 - Finite State Machine

FSM verilog example

FINAL Lab - The Laundry Washing Machine Display Controller

Lab Final - Laundry Washing Machine

 Chapter 8.4 - Digital Systems Design  - Mano & Ciletti.

FSM Tutorial (.pdf)

EE2169 Final Lab Presentation

      

ASIC World - Verilog HDL Tutorial and Examples

Introduction to Verilog - P.M. Nyasulu  

NI ELIVS II Orientation Manual

NI Digital Electronics FPGA Board - User Manual  

NI Labview Environment Tutorial

Spartan 3E DEFB User Constraints File Template

BASYS UCF Template

Xilinx ISE Design Software Download

Xilinx ISE Basic Schematic Input Tutorial (Youtube)

Xilinx ISE Getting Started and iMPACT Tutorial (pdf)

Xilinx ISE Verilog HDL Tutorial (Youtube)

Xilinx Test Bench Tutorial (pdf)

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