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EE2169 Laboratory for Digital Systems Design I

Welcome to Summer 2018 Class

These WIKI pages provide instructions, assignments, and supplemental information for the laboratory sections of EE2369, Digital Systems Design I.

Office Hours of Teaching Assistants

     - Basavarajaiah Totada:                           Monday to Thursday  2:30PM - 3:30PM


Lab Rubric Summer 2018


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Laboratory Information

EE2169 Syllabus Summer 2018


Laboratory Assignments

Lab1 - Binary Number Systems                             

Lab2 - Switches and LEDs                                     

Lab3 - Logic Expressions                                      

Lab4 - Logic Gates                                              

              7404 datasheet

              7408 datasheet

              7432 datasheet

Lab 5 – Logic Circuit in Xilinx ISE                         

Lab 6 - Number-to-Braille Encoder Design           

Lab 7 - Number-to-Braille Verilog-VHDL                

Lab#8 - Full Adder with BCD Display                  

             Lab#8 Header Verilog

             Lab#8 Header VHDL

Lab#9 Add Sub & Shift Reg                                 

             lab9_HeaderSample (.v file)

             Lab9_Constraints     (.ucf file)

Lab#10 Finite State Machine                                

Lab#11 ASM HAWK                                              

Lab#12 ASM Traffic Light w Ped                           



 

    Sequential Logic Implementation

      

ASIC World - Verilog HDL Tutorial and Examples

Introduction to Verilog - P.M. Nyasulu  

NI ELIVS II Orientation Manual

NI Digital Electronics FPGA Board - User Manual  

NI Labview Environment Tutorial

Spartan 3E DEFB User Constraints File Template

BASYS UCF Template

Xilinx ISE Design Software Download

Xilinx ISE Basic Schematic Input Tutorial (Youtube)

Xilinx ISE Getting Started and iMPACT Tutorial (pdf)

Xilinx ISE Verilog HDL Tutorial (Youtube)

Xilinx Test Bench Tutorial (pdf)

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