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EE2169 Laboratory for Digital Systems Design I

Welcome to Spring 2018 Class

These WIKI pages provide instructions, assignments, and supplemental information for the laboratory sections of EE2369, Digital Systems Design I.

Office Hours of Teaching Assistants

     - Basavarajaiah Totada:                           Monday and Wednesday  10:30AM - 12:30PM

     - Maryamsadat Shokrekhodaei :             Wednesday  9:30AM - 10:30AM

                                                                       Thursday      9:00AM - 11:00AM

                                                                       Friday           9:30AM - 10:30AM

     - Maher Aldeghlawi:                                Monday and Thursday 10:30AM - 12:30PM

Lab Rubric Spring 2018


Announcement: (week of 3/25/2108 - 3/30/2018)

No lab assignment for this week. these lab sessions are makeup sessions.

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Laboratory Information

EE2169 Syllabus Spring 2018


Laboratory Assignments

Lab1 - Binary Number Systems                             (Due 1/22/2018 - 1/26/2018)

Lab2 - Switches and LEDs                                     (Due 1/29/2018 - 2/2/2018) 

Lab3 - Logic Expressions                                       (Due 2/5/2018 - 2/9/2018)

Lab4 - Logic Gates                                                 (Due 2/12/2018 - 2/16/2018)

              7404 datasheet

              7408 datasheet

              7432 datasheet

Lab 5 – Logic Circuit in Xilinx ISE                          (Due 2/19/2018 - 2/23/2018)

Lab 6 - Number-to-Braille Encoder Design            (Due 2/26/2018 - 3/2/2018)

Lab 7 - Number-to-Braille Verilog-VHDL                (Due 3/5/2018  - 3/9/2018)

Lab#8 - Full Adder with BCD Display                     (Due 3/19/2018 through 3/23/2018)

             Lab#8 Header Verilog

             Lab#8 Header VHDL

Lab#9 Add Sub & Shift Reg                                   (Due 4/2/2018 through 4/6/2018)

             lab9_HeaderSample (.v file)

             Lab9_Constraints     (.ucf file)

Lab#10 Finite State Machine                                 (Due 4/9/2018 through 4/13/2018)

Lab#11 ASM HAWK                                               (Due 4/16/2018 through 4/20/2018)

Lab#12 ASM Traffic Light w Ped                            (Due 4/23/2018 through 4/27/2018) 



 

                                          


11/8/2017 Lecture notes - FSM - traffic light



Lab Final - Car Wash


Sequential Logic Implementation

      

ASIC World - Verilog HDL Tutorial and Examples

Introduction to Verilog - P.M. Nyasulu  

NI ELIVS II Orientation Manual

NI Digital Electronics FPGA Board - User Manual  

NI Labview Environment Tutorial

Spartan 3E DEFB User Constraints File Template

BASYS UCF Template

Xilinx ISE Design Software Download

Xilinx ISE Basic Schematic Input Tutorial (Youtube)

Xilinx ISE Getting Started and iMPACT Tutorial (pdf)

Xilinx ISE Verilog HDL Tutorial (Youtube)

Xilinx Test Bench Tutorial (pdf)

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