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EE2169 Laboratory for Digital Systems Design I

Welcome to Fall 2017 Class

These WIKI pages provide instructions, assignments, and supplemental information for the laboratory sections of EE2369, Digital Systems Design I.

Check The course Syllabus for the updated office hours


Laboratory Information

EE2169 Syllabus fall 2017 

Laboratory Assignments

Lab1 – Binary Number Systems        (due 9/5/2017 -  9/8/2017) 

Lab2 – Switch and LED Logic            (due 9/--/2017 - 9/–/2017)

Lab3 – Logic Expressions                  (due 9/18/2017 - 9/22/2017)

Lab4 – Basic Logic Gates                   (due 9/26/2017 - 9/29/2017)

            7404 datasheet

            7408 datasheet

            7432 datasheet

Lab5 – Logic Circuit in Xilinx ISE          (due 10/3/2017 - 10/6/2017)

Lab6 – Numeric Braille Writer               (due 10/10/2017 - 10/13/2017)

Lab 7 - Universal Gates                        (due 10/17/2017 - 10/20/2017)

Lab8 – Numeric Braille Writer with Verilog       (due 10/24/2017 - 10/27/2017)

            Lab8 Header Verilog

            Lab8 Header VHDL

Lab7 – Full Adder and BCD to 7-segment Decoder           (due Mon 9/26/2017)

           LAB7_HeaderSample (.v file)

           Lab7_Constraints   (.ucf file)


           Lab_8b (.v)

           Lab_8a_Constraints (.ucf file)

           Lab_8b_constraint (.ucf file)

Lab9 – Finite State Machine


LabFinal – The Burrito Vending Machine

                     A Design Example - Traffic Lights 

                        Sequential Logic Implementation


ASIC World - Verilog HDL Tutorial and Examples

Introduction to Verilog - P.M. Nyasulu  

NI ELIVS II Orientation Manual

NI Digital Electronics FPGA Board - User Manual  

NI Labview Environment Tutorial

Spartan 3E DEFB User Constraints File Template

BASYS UCF Template

Xilinx ISE Design Software Download

Xilinx ISE Basic Schematic Input Tutorial (Youtube)

Xilinx ISE Getting Started and iMPACT Tutorial (pdf)

Xilinx ISE Verilog HDL Tutorial (Youtube)

Xilinx Test Bench Tutorial (pdf)

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